1. Field of the Invention
The present invention relates to the art of testing a semiconductor integrated logic circuit and, more particularly, to a scan path circuit for use in a function test of a sequential circuit.
2. Description of the Related Art
As constant efforts are made to achieve higher integration of semiconductor integrated logic circuits, more difficulty is experienced in testing the functions of these circuits. Generally, integrated logic circuits are sequential circuits and, one known method employed to facilitate the test of such a sequential circuit, is the Scan Path method in which the sequential circuit to be tested is first divided into storage elements such as flip-flops and latches, and a combinational circuit to form a scan path circuit. The storage elements are then rearranged to operate as a shift register with the combinational circuit.
FIG. 1 of the accompanying drawings shows a conventional scan path circuit. Data input signals and clocks signals to be supplied to flip-flops 1 through 4 are selected respectively by first selectors 5 through 8 and second selectors 9 through 12. More specifically, during normal operation, signals from a combinational circuit 13 are supplied as data input signals and clock signals to the flip-flops 1 through 4. In the scan path test, a scan switching signal 14 is applied to the first selectors 5 through 8 to switch from the signals from the combinational circuit 13 to a signal from the scan-in terminal 15 and signals from Q output terminals of the preceding flip-flops. At the same time, a clock switching signal 17 is applied to the second selectors 9 through 12 to supply a common clock signal 16 to the flip-flops 1 through 4, which now operate as a shift register.
A test pattern signal is applied from the scanning terminal 15, and the clock signal 16 is applied to establish values stored in the flip-flops 1 through 4. The values stored in the flip-flops 1 through 4 are successively output from a scan-out terminal 18. The output values from the scan-out terminal 18 are compared with a pattern of expected values. In this manner, the sequential circuit is tested.
In the conventional scan path circuit, the clock signal may be applied to the flip-flops at different times because of the uneven layout of clock signal lines for each flip-flop of the shift register, buffers inserted to compensate for the insufficient driving capability of the clock signal, and so on. Thus, in the scan path test, the flip-flops read the data input signals at different times, resulting in the failure to operate properly as a shift register. It has been quite difficult to design clock signal timing for the purpose of avoiding the above problems.